A variety of systems make use of multiple cores such as the cores of a multi-core processor. The cores are each based on reduced instruction set computing (RISC) architectures such as the ARM (Advanced RISC Machine) architecture. When debugging these systems, a debug controller can be connected to the system through a port such as a JTAG debug port. The port generally places the debug controller in communication with a debug bus that is also in communication with each of the cores. In the ARM debug architecture, the debug controller and the cores are arranged in a bus topology.
During the debug process, the debug controller uses this debug bus to access various debug resources on the different cores for various transactions such as read and write. When the cores are ARM cores, the debug bus is also used for other sideband functions related to the debugging process. For instance, the debug bus can carry authentication signals that allow or disallow operation of various debug features. As the number of cores in communication with the debug bus increases, implementing the various different functions of the debug bus becomes a challenge due to the increasing number of bus wires that are required to implement these sideband functions.
Additionally, a debug architecture and/or a debug specification specifies which resources can be accessed during the debug process. However, during the debug process, it is often useful and/or desirable to access resources that the debug architecture does not identify as being accessible. Since these resources are not specified as being accessible, they cannot be accessed over a debug bus operating according to the debug specification.
There is a need for a debug system that can provide a debug controller with efficient access to resources within an increasing number of ARM cores. Additionally or alternately, there is a need for a mechanism for accessing resources that a debug architecture and/or a debug specification does not identify as being accessible over a debug bus.